The control over transfer of data between a storage unit of a central processing unit and peripheral I/O devices over an input/output bus, or interface, can take many forms. Among the forms of input/output control for the purpose of data transfer are: direct program instruction control for each transfer of data, the initiation of data transfers by a central processor after which subsequent data transfer is accomplished under control of the peripheral device without use of the central processor, and logic for handling interrupt requests from peripheral devices to inform the central processor of peripheral device status. Included in several of these forms are control mechanisms for permitting peripheral I/O devices to initiate interrupt handling in the central processor by directly informing the processor of the device and status requiring handling. The interrupt request may require the central processor to initiate a polling signal to all attached devices, in series, to subsequently permit information to be transferred to the central processor identifying the device and status causing the interrupt. Such a polling technique is described in U.S. Pat. No. 4,038,642 issued to Bouknecht et al on July 26, 1977 and entitled "Input/Output Interface Logic for Concurrent Operations."
Previously existing I/O controllers, such as the controller described in the Bouknecht et al Patent are intended for use with a single I/O device. Such a controller only recognizes a single device address. Additional previously existing I/O controllers are used with multiple I/O devices, in which case, an address compare circuit is necessary to recognize the multiple device addresses. The recognition of multiple device addresses is necessary since there are different device addresses for each of the different I/O devices connected to the controller. In these prior art systems, the receipt of a proper device address is applied to the controller and also indicates to the controller which particular I/O device is being addressed.
Previously developed prior art controllers are not primarily useful for multiple I/O devices which have a single device address. Two problems are particularly associated with the use of an I/O control unit which recognizes or responds to a single I/O control unit address where the control unit has multiple I/O devices connected thereto. The nature of the first problem is that requests for service from the I/O devices are asynchronous in nature, such as operator requests from terminals, and may result in excessive interrupts to the processor, thereby reducing responsiveness to service requests during periods of high interrupt activity. A second problem is that requests for service from I/O devices can tie up the control unit to create a busy, interrupt pending, status and thereby prevent operations in response to service requests for those I/O devices which have already had their requests accepted by the processor.
A need has thus arisen for an I/O controller to pace the presenting of interrupts from asynchronous multiple I/O devices to a host processor and to reduce such interrupts during periods of high input/output device request activity. A need has further arisen for an I/O controller which increases control unit availability to a host processor I/O program and therefore, I/O device availability, by preventing I/O controller busy, interrupt pending, reporting to the host processor I/O command in high activity situations where the control unit would normally be attempting to field many interrupts into the host processor.